[Open_electroporator] culture shock ADC and DMA

John Griessen john at cibolo.com
Wed May 30 20:30:28 UTC 2018


On 05/30/2018 02:53 PM, Nathan McCorkle wrote:
> John, can you tell me what voltage I should feed into the high-side to be under that limit in a max-pulse-power situation?

After a couple of days of this, I see so much non-intuitive results that I cannot see a limit by merely keeping the DC input to 
the switcher low.  The main thing that makes HV is close spaced pulses. (if they are transferring charge through the doubler).

If you try very close spaced pulses,  a(50,14,15)
https://www.cibolo.com/docs/kvboard_pyflex_f401_v0.5_tests-2.jpg
the result is unimpressive.

Longer is better for getting big HV:
a(69,22,19)    https://www.cibolo.com/docs/kvboard_pyflex_f401_v0.5_tests-3.jpg
The above photo had some different HV diodes so it had lots of spikes, and average was lower, but spikes go to 2500V briefly.

After using 3kV through hole diodes:    a(69,22,19)

https://www.cibolo.com/docs/kvboard_pyflex_f401_v0.5_tests-4.jpg

Next I tried a(74,14,39)  narrower width to stop sucking so much power and keep a flat top:

https://www.cibolo.com/docs/kvboard_pyflex_f401_v0.5_tests-6.jpg

and the same thing via the volt divider instead of my P6009 probe:

https://www.cibolo.com/docs/kvboard_pyflex_f401_v0.5_tests-7.jpg





There is a limit to how close spaced they can be and still work, then the transferred energy is less and HV goes down.

The doubler diodes and capacitors have a resistive component, so the doubler is a low pass filter.

The v0.5 culture shock machine is packed and so I now need to build another one to test with, but have some house chores first.


I think trying a 12V wall wart and keep the pulse period number above 70 always, and experiment with shorter
width numbers like 10 8 6 to transfer less and sometimes larger period numbers too if not minding the jagged shapes you get.


Later on I may be able to make a slight improvement in jagged shape (and overall speed) by the FET gate drivers
going to CMOS instead of NMOS with 220 ohm pullups as is now.  Testing some of the other transformers could maybe go faster too.

Looking at https://www.cibolo.com/docs/kvboard_pyflex_f401_v0.5_tests-7.jpg
you see it takes 5 push/pull cycles to get up to 2200V.  We need to live with that for now, as you plan the feedback loop.
Make sure your feedback gain is low enough to stop it from zooming in 0.1 ms.  Some feed forward can be added to help make crisp
rise times, after getting a stable non-oscillating feedback, (and knowing the cuvette R value).  (Feedback wants to oscillate 
analog or digital just the same.)

-- 
John


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